| Title |
Formation of Sn Through-Silicon-Via and Its Interconnection Process for Chip Stack Packages |
| Authors |
김민영(Min Young Kim); 오태성(Tae Sung Oh); 오택수(Taek Soo Oh) |
| DOI |
https://doi.org/10.3365/KJMM.2010.48.06.557 |
| ISSN |
1738-8228(ISSN), 2288-8241(eISSN) |
| Keywords |
electronic materials; joining; strength; scanning electron microscopy; microelectronic packaging |
| Abstract |
Formation of Sn through-silicon-via (TSV) and its interconnection processes were studied in order to form a three-dimensional interconnection structure of chip-stack packages. Different from the conventional formation of Cu TSVs, which require a complicated Cu electroplating process, Sn TSVs can be formed easily by Sn electroplating and reflow. Sn via-filling behavior did not depend on the shape of the Sn electroplated layer, allowing a much wider process window for the formation of Sn TSVs compared to the conventional Cu TSV process. Interlocking joints were processed by intercalation of Cu bumps into Sn vias to form interconnections between chips with Sn TSVs, and the mechanical integrity of the interlocking joints was evaluated with a die shear test. |