| Title |
A Flip Chip Process Using an Interlocking-Joint Structure Locally Surrounded by Non-conductive Adhesive |
| Authors |
최정열(Jung Yeol Choi); 오태성(Tae Sung Oh) |
| DOI |
https://doi.org/10.3365/KJMM.2012.50.10.785 |
| ISSN |
1738-8228(ISSN), 2288-8241(eISSN) |
| Keywords |
Electrical/electronic materials; joining; electrical properties; electrical conductivity/resistivity; flip chip |
| Abstract |
A new flip chip structure consisting of interlocking joints locally surrounded by non-conductive adhesive was investigated in order to improve the contact resistance characteristics and prevent the parasitic capacitance increase. The average contact resistance of the interlocking joints was substantially reduced from 135mΩ to 79mΩ by increasing the flip chip bonding pressure from 85MPa to 185MPa. Improvement of the contact resistance characteristics at higher bonding pressure was attributed not only to the increased contact area between Cu chip bumps and Sn pads, but also to the severe plastic deformation of Sn pads caused during formation of the interlocking-joint structure. The parasitic capacitance increase due to the non-conductive adhesive locally surrounding the flip chip joints was estimated to be as small as 12.5%. |