| Title |
Effect of Polishing Process of a Semiconductor Wafer on the Fracture Mechanics of Diced Chips |
| DOI |
https://doi.org/10.3365/KJMM.2016.54.3.204 |
| ISSN |
1738-8228(ISSN), 2288-8241(eISSN) |
| Keywords |
semiconductor; silicon wafer; chip; fracture; reliability |
| Abstract |
This article shows how the adoption of polishing as the back-lapping process of semiconductor wafers influences the flexural fracture strength of their individually diced chips. According to the experimental results of this study, a polishing powder with a particle size of approximately 1 um in diameter can meaningfully reduce the fracture strength of chips with a thickness of 50 um. Particularly, when the diced chips have polishing-induced defects formed along a (110)-dicing plane, they reveal the lowest fracture strength. An in-situ examination details how polishing causes sharp notches on the back surface of the chips which provide preferential sites for chip cracking during a flexural test. |